Introduction to the Open Verification Methodology (OVM)

This 4 day course is for engineers interested in developing SystemVerilog verification environments using the latest Open Verification Methodology (OVM).

Students will first learn:

  • Basic testbench structure
  • How to model communication at the transaction level (TLM)
  • How to write analysis components such as Scoreboards and Coverage Collectors
  • Strategies for connecting to RTL designs including
  • How to integrate and use the UVM Register package into an OVM testbench

After mastering the basics, students will learn best-practice techniques to maximize the reusability of their test environments. Topics include:

  • Using the OVM factory
  • Managing complexity using hierarchy and factory overrides
  • Making reusable testbenches
  • Developing test cases using OVM sequences


Syllabus

  • Introduction to OVM
  • Transaction-level Communication
    • TLM Interfaces
    • TLM Channels
    • Port & Exports
  • Basic Testbench Structure
    • Components
    • Phasing
    • Start and end of simulation
  • Dynamic Construction - Introduction to the OVM Class Factory
  • Connecting to the DUT
  • Generating Reports and Messaging
  • Modeling Transactions
  • Analysis 
    • OVM Analysis components
    • Scoreboards, coverage collectors, predictors
  • Hierarchy
    • OVM Components and Hierarchy
    • Hierarchical API
  • Creating a Configurable Test Environment
    • Factory Overrides
    • Configurations
  • Stimulus generation
    • Sequences
    • Scenarios (testing patterns)
  • The UVM Register Package
    • Understanding a Register Model
    • Integrating a Register Model
    • Using a Register Model

Hands-On Labs

A good portion of class time will be spent applying principles learned in lecture to hands-on labs

Prerequisites

WHDL SystemVerilog for Verification course or equivalent experience using SystemVerilog

Class Dates & Locations

Begin Date End Date Location Enroll
There are no scheduled classes available.