SystemC Modeling with TLM 2.0
This four-day workshop introduces the student to the SystemC C++ class library and the TLM 2.0 modeling standard. It is intended for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC for modeling purposes.
The student will learn how to write, compile, execute and debug system and hardware descriptions with SystemC, as well as a thorough and in-depth coverage of the concepts of the OSCI TLM 2.0 modeling standard.
This course is mixed lecture and exercises, with an exercise for nearly every topic.
Introduction to SystemC
-
Core
Library Basics
- Modules
- Communication (channels, ports & exports)
- Module Constructor (+ exercise)
- Simulation
- Scheduler
- Events & Event Queues
-
Modeling Behavior
- Method processes (+ exercise)
- Thread processes (+ exercise)
- Module instantiation (in module) (+ exercise)
- Simulation Initialization
-
Core
Library Elements
- SystemC data types
- Primitive channels
-
User
defined channels (+ exercise)
- Custom Constructors
- Exports
- Dynamic Processes (+exercise)
Introduction to the OSCI TLM 2.0 Standard
-
TLM 2.0 Overview
- Interface functions
- Sockets
- Generic payload
- Protocol
-
Interfaces
- Transport
- DMI
- Debug
-
Sockets
- Initiator and target
- Socket binding
- Hierarchy, multi-connect
- Topology examples
-
Generic Payload Overview
- Attributes
-
LT Coding style (+exercise)
- Transport interface
- Temporal decoupling
- Quantum Keeper
-
AT Coding Style (+exercise)
- Protocol phases
- Forward, backward, and return paths
- Base protocol (2-phase)
- Payload Event Queue (PEQ)
-
DMI interface
- DMI hint
- DMI data structure
- Invalidating DMI
-
Debug Interface (+exercise)
- Debug Transport interface
-
Convenience Sockets (+exercise)
- Simple sockets
- Tagged sockets
- Multi-passthrough sockets
-
Generic Payload In-depth
- Byte Enable
- Streaming
- Endianness
- Memory management
- Generic Payload Extensions (+exercise)
-
Base Protocol In-depth
- 4-state and variants