Advanced VHDL

A 3 day course emphasizing behavioral techniques, testbench strategies and design management.

The 3-day Advanced VHDL class is aimed at experienced VHDL users who wish to take their use of the language to a higher level. The course is a consistant mix of lecture and lab-exercises.

A pre-requisite for this course is the Introduction to VHDL course or equivalent experience.

Syllabus

• Advanced VHDL language topics
• Access type
• Dynamic memory allocation
• Resolution Functions
• Shared variables
• Guarded blocks
• File I/O
• Behavioral modeling
• Thinking Behaviorally
• Basic algorithms
• Data Structures
• System modeling
• Handshaking/protocol techniques
• Functional Verification
• Stimulus generation techniques
• Random stimulus generation
• LFSR models
• External files
• Sweepers
• Verification using signatures
• High-level debugging using Monitors
• Design Management
• Using Makefiles
• Automating compilation/verification
• Source Code Control
• Intro to RCS

Prerequisites

Our Introduction to VHDL training course or equivalent experience.