Advanced SystemC Verification
This three-day workshop is intended for engineers who are familiar with SystemC with an interest in using SystemC for Advanced Verification.
This three-day workshop focuses on verification and test bench techniques using SystemC and the SystemC Verification Library.
Syllabus
- Verification concepts
- Testbench structure
- Testbench strategies
- Stimulus generation
- Transaction-based stimulus
- Constrained randomization of data
- Randomizing control flow
- Dynamic construction with parameters
- Using dynamic processes for stimulus
- Transactors
- Mixed-language simulation (tool specific)
- Verification
- Shadow models
- Monitors
- Assertions
- Checkers
- Analysis
- Intro to C++ Standard Template Library
- Applying STL: Scoreboards
- Transaction-level logging / viewing
- Coverage
- Code / line coverage (tool specific)
- Functional coverage (tool specific)
- Reactivity
- Closing the loop: feedback to stimulus
- Intro to C++ Standard Template Library
Hands On Labs
A good proportion of class time will be spent on practical lab exercises.
Prerequisites
Introduction to SystemC for Verification training course (or equivalent experience).