SystemVerilog Open Verification Methodology (OVM)

This 3 day course is for engineers interested in developing SystemVerilog verification environments using the Open Verification Methodology (OVM).

Students will first learn:

  • Basic testbench structure
  • How to model communication at the transaction level (TLM)
  • How to write analysis components such as Scoreboards and Coverage Collectors
  • Strategies for connecting to RTL designs including
    • SystemVerilog Interfaces
    • API-driven bus-functional models (BFMs)

After mastering the basics, students will learn best-practice techniques to maximize the reusability of their test environments. Topics include:

  • Using the OVM factory
  • Managing complexity using hierarchy and factory overrides
  • Making your components reusable with the OVM configuration API
  • Managing test cases using OVM scenarios and sequences


Syllabus

  • Introduction to OVM
  • Transaction-level Communication
    • TLM Interfaces
    • TLM Channels
    • Port & Exports
  • Basic Testbench Structure
    • Components
    • Threaded_component
    • Environment
    • Phases
  • Dynamic Construction - Introduction to the OVM Class Factory
  • Connecting to the DUT
    • Transactors
    • Virtual Interfaces
    • Working with BFMs
  • Generating Reports and Messaging
  • Modeling Transactions
  • Adding Analysis Components
    • Analysis components
    • Scoreboards
    • Coverage Collectors
    • Control Blocks
  • Hierarchy
    • OVM Component and Hierarchy
    • Hierarchical API
  • Creating a Configurable Test Environment
    • Factory Overrides
    • Configuration
  • Managing Test cases
    • Layered Stimulus (Scenarios)
    • Programmable Transaction Sequences
  • Other OVM Classes
  • Mixed Language Simulation
    • Using SystemC TLM models in a SystemVerilog Test Environment
  • Design Patterns

Hands-On Labs

A good portion of class time will be spent applying principles learned in lecture to hands-on labs

Prerequisites

WHDL SystemVerilog for Verification course or equivalent experience using SystemVerilog

Class Dates & Locations

Begin Date End Date Location Enroll
There are no scheduled classes available.