Introduction to SystemC for Modeling
A three-day workshop for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC for modeling purposes.
This three-day workshop introduces the student to the SystemC C++ class library. It is intended for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC for modeling purposes. Verification will be touched only lightly. The student will learn how to write, compile, execute and debug system and hardware descriptions with SystemC. This course is mixed lecture and exercises, with an exercise for nearly every topic.
Syllabus
- Introduction
- SystemC modeling
- Basic modeling structure
- Getting started - running & debugging
- Modules
- Channels, ports, interfaces
- Module constructor
- Events
- Processes in general
- Thread processes
- Method processes
- Module instantiation (in modules)
- sc_main
- SystemC data types
- Primitive channels
- User defined channels
- Introduction to the TLM standard
- Introduction to SystemC Verification Library
Hands-On Labs
A good portion of class time will be spent applying principles learned in lecture to hands-on labs
Prerequisites
- Introduction to C++ (2 days) training course
- Course may be taken immediately before this course
- Course may be taken immediately before this course
Class Dates & Locations
| Begin Date | End Date | Location | Enroll |
|---|---|---|---|
| There are no scheduled classes available. | |||