Assertion Verification with PSL
This 2-day class is designed for users of Verilog and VHDL who want to learn about Assertion Based Verification using PSL.
PSL is a widely accepted standard for defining properties of a design which can be evaluated
during simulation as well as by other verification tools like Formal. The class introduces the student o the syntax of PSL but much more importantly describes how to incorporate Assertion
Based Verification ( PSL assertions and coverage ) into your verification strategy.
The format of the class is mixed lecture/lab, with lab exercises immediately following each major topic. The lab exercises are intended to reinforce the preceding lecture topic(s).
The class is taught using ModelSim from Mentor Graphics but is applicable to other simulators
supporting the PSL spec.
Syllabus
- Introduction to Assertion Based Verification
- Assertions & Languages
- Getting Started
- Simple Assertions
- Boolean Expressions
- Clocking
- Implication
- More Complex Assertions
- Strong & Weak operators
- Longer Sequences
- SEREs
- Implication
- Repetition
- Verification Units
- Modeling Layer
- A PSL Methodology
- Case Study - UART
Prerequisites
Prior experience with Verilog/VHDL is required.
Class Dates & Locations
| Begin Date | End Date | Location | Enroll |
|---|---|---|---|
| There are no scheduled classes available. | |||