We offer a broad range of courses and each one can be customized to best match the needs of your team. All courses are available for onsite instruction (5 student minimum). Most are also offered regularly at our training center in Beaverton OR.

SystemVerilog Courses

SystemVerilog for Verification
This 4 day course is aimed at experienced Verification engineers who wish to learn about verification with SystemVerilog.

SystemVerilog Assertions (SVA)
This one day course is targeted at Design and Verification engineers who wish to deploy Assertion based Verification within their next project.

SystemVerilog Open Verification Methodology (OVM)
This 3 day course is for engineers interested in developing SystemVerilog verification environments using the Open Verification Methodology (OVM).

SystemC Courses

Introduction to SystemC for Modeling
A three-day workshop for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC for modeling purposes.

Introduction to SystemC for Verification
This three-day workshop introduces the student to the SystemC C++ class library and to the SystemC Verification library.

Advanced SystemC Modeling
This two-day workshop is intended for engineers who are familiar with SystemC with an interest in learning more about the TLM standard and advanced SystemC modeling.

Advanced SystemC Verification
This three-day workshop is intended for engineers who are familiar with SystemC with an interest in using SystemC for Advanced Verification.

Introduction to C++
WHDL offers several Introduction to C++ courses. Choose a course based your programming experience with C++.

Other HDL Courses

Introduction to Verilog for RTL Design
A 3 day course teaching designers to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques.

Introduction to VHDL for RTL Design
A 4 day course teaching designers to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques.

Advanced VHDL
A 3 day course emphasizing behavioral techniques, testbench strategies and design management.

Assertion Verification with PSL
This 2-day class is designed for users of Verilog and VHDL who want to learn about Assertion Based Verification using PSL.

Support Languages

Introduction to Perl
This 2 day class will introduce the student to the Perl programming language.

Introduction to TCL/TK
This 2 day class will introduce the student to the TCL programming language and to the GUI capabilities of the Tk toolkit.